第十一低功耗.pptx

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1、Why Low PowerPotable system-Battery lifetimeExample:mobile phone,PDA,Digital cameraDesktops:high power consumptionReliability and performanceNeed expensive chip package,cooling systemSeveral deleterious effectsDecreased reliability and performanceIncreased cost:packaging cost and cooling systemExcee

2、d power limits of the chip&system第1页/共54页Power,Cost and HeatComponent:silicon and packageIncreased die size(wider power busses)Need better thermal capabilities(package material)Need better electrical capabilities System:Cooling and mechanicalsLarger fansOversized power suppliesPower limits to the wa

3、ll1100W dc limit for 110V/20A plug第2页/共54页Challenge of Design as Process Scaling第3页/共54页OutlineWhy low powerSources of power consumptionLow power design methodologyLow power techniques Power analysis and toolsTrends in the future第4页/共54页Source of Power ConsumptionDynamic power consumptionStatic powe

4、r consumptionKey areas of power consumption in SOC第5页/共54页Source of Power Dissipation in CMOS DevicesC =node capacitancesNsw=switching activities (number of gate transitions per clock cycle)F =frequency of operationVDD =supply voltageQsc =charge carried byshort circuit currentper transitionIleak =le

5、akage current第6页/共54页Static Power Consumption:Leakage currents:Sub-threshold current(I2)Gate leakage Gate tunnelling(I4)Gate induced drain leakage(I3)pn-junction reverse current(I1)DC currentsAnalog circuit:sense-amps,pull-upsState dependent第7页/共54页Leakage vs.ProcessWhat will be the dominated leakag

6、e current?Long Channel(L1um)Very small leakageShort channel(L180nm,tox30A)Subthreshold leakageVery short channel(L90nm,tox20A)subthreshold+gate leakageNano-scaled(L90nm,Tox20A)Subthreshold+gate+junction leakageSub-threshold leakage current Has become quite important with technology scalingGate leaka

7、ge currentIs becoming important with shrinking device dimensions PN junction leakage currentNegligible 第8页/共54页OutlineWhy low powerSources of power consumptionLow power design methodologyLow power techniques Low power analysis and toolsTrends in the future第9页/共54页Low Power Design MethodologyMust kno

8、w your systemMaximize the performance while minimize the power consumptionMinimize the power consumption while maximize the performance第10页/共54页Opportunities for Power Saving第11页/共54页OutlineWhy low powerSources of power consumptionLow power design methodologyLow power techniques Power analysis and t

9、oolsTrends in the future第12页/共54页Low Power TechniquesLeakage power controlDynamic power controlArchitecture level power optimizationSystem level power optimization第13页/共54页Low Power TechniquesProcess scaling Low Vdd,Multi-thresholdVoltage scalingSubstrate bias(200mv)Multi-voltage(voltage island)Dyna

10、mic voltage scaling;multi-thresholdHW design techniquesPre-computation,glitch minimization,Logic level,Physical level optimizationLow power System/SW Power aware Operation System,compiler,SW design etc.第14页/共54页Low Power Techniques on Chip DesignLeakage PowerMulti Vt optimizationPower gatingSubstrat

11、e biasPower gatingDynamic PowerMulti-voltage designAdvanced clock-gatingGate-level power optimization第15页/共54页Techniques for Reduce Leakage Power第16页/共54页Using Multi-Vt LibrariesTiming and leakage tradeoffLow Vt cell:faster speed,high leakageHigh Vt cell:slower speed,lower leakagePrinciple:low Vt fo

12、r critical path and high Vt for non-critical pathsHigh Vt cell on Critical PathHints:1.You need to have dual Vt library2.You need to pay for the extra layer mask for multi-vt 第17页/共54页Using Multi-Vt Libraries cont.Synthesis Strategy:Use high Vt cells first,then fix setup violation by replace the hig

13、h Vt cells on the critical path to low Vt cellsUse low Vt cells first,then swap to high Vt cells,fix setup violation by swap low Vt cells on the pathsNo area penalty Library design for freely mix and match on SoC design第18页/共54页Power Gating Also called Multi-Threshold CMOS(MTCOMS),logic sleep contro

14、l,etc.Active mode:sleep control devices on,VDDV and GNDV act as virtual supplySleep mode:sleep control devices off,reduce leakageHigh Vt transistors reducing both leakage and switching power第19页/共54页Power Gating cont.Sleep transistors used only on the supply rail or on both supply and ground railsNo

15、t added on every gatePower gating retention registerActive modeHigh performance regular FF functionSleep ModeCut-off VddLow leakage stage saving latch function第20页/共54页Body BiasVariable threshold according to body biasingZero body bias in active mode(Low Vt)Reverse body bias in stand-by mode(High Vt

16、)Tradeoff between the time on module turn-on and leakage currentTriple well structure CMOS InverterHint:Do you have the triple well structuredstandard cell lib?第21页/共54页Techniques for Reduce Dynamic Power第22页/共54页Multi Voltage DesignBlock based approach in the design flowNeed to additional isolation

17、 cells and voltage level-shifter cells between voltage domains第23页/共54页Clock Gating TechnologyToggling consume power.Enable the module clock only when neededgated_clkEnableLogicGlobalClkComb.LogicDataReg第24页/共54页Clock Gating Cell DesignProblem with simple clock gating:Uncompleted cycleGlitch第25页/共54

18、页Clock Gating with LatchAdd a transparent-low latchMake sure the clk gating cells are placed tightly for correct function clk cell hardeningCommonly in SoC:make a“hardmacro”-clk gating cellRTL code for clk cell:always(clk or clk_en)if(!clk)ctrl_latch=clk_en;assign gclk=ctrl_latch&clkClock gating cel

19、ls and a glitch free clock gating第26页/共54页Clock Gating With Integrated Test LogicAbility to let clk pass through in test mode (TEST=1)第27页/共54页Gated Clock in Clock Tree DesignDisable clocking near the root of a clock tree,instead of at each FF.Special care must be taken in clk tree synthesis to prev

20、ent the buffers inserted between clk root and the clk gating cell第28页/共54页Gate Level OptimizationTechnology independent optimization:Circuit optimization:logic optimization,reduce redundant logicTrimming for low power:reduce positive slackGate resizingPin swapping/reassignmentRe-mappingPhase assignm

21、entRe-factoringLow power driven technology mappinglow power cell第29页/共54页Gate Level Optimization Gate SizingGate sizingDown-size gates on fast paths to decrease their input capacitances for minimizing switching current in front driver Enlarge heavily loaded gates to increase their output slew rates

22、for minimizing short-circuit current第30页/共54页Dealing with GlitchesFor some type of data path circuits,up to 60%of the dynamic power is due to glitchesVery expensive calculationNeed to propagate probabilistic waveforms第31页/共54页Example:Glitch MinimizationHazardous transition occurs at the output of AN

23、D gate due to different delays through two different delay paths converging at the inputs to the gate第32页/共54页Physical Level OptimizationLibrary Design:Energy-efficient cells Design planning:develop a realizable floorplan and realistic budgets for powerPlacement and routing:reduce glitchesIn placeme

24、nt optimization:buffer&wire resizing Transistor resizing:minimize capacitanceWidth/Spacing/Shielding/Metal layer optimization to reduce C&R.Reduce via resistance by adding more vias第33页/共54页Physical level optimization cont.Power planning:defines power rings and mesh.Power driven floor-planningDecoup

25、ling cap between Supply and GroundSudden change in power consumption occur when blocks are powered on or offDecoupling capacitor helps to reduce the transient current for high speed designHave seen in filler cell at 0.13um processBut the leakage on decoupling cap itself at 90nm and below must take i

26、nto account第34页/共54页Global Clock RoutingReduce Clock LoadnReduce oversized clock drivernReduce#of clock driversnReduce#of clock tracksMinimum Width Clock Tracks are resistance limitednLower R for drivabilitynLower C for powernIncrease width&space to minimize C&R where possible.nAdd enough vias to re

27、duce resistance第35页/共54页Architecture level Power OptimizationMemory OptimizationParallel/Pipeline Algorithm第36页/共54页Memory OptimizationMemory cell redesignReduce leakageDual Vt SRAM CellGated Vdd SRAM cellGated GND SRAM cellPower-aware DRAMMemory hierarchySmall segmentEach bank can independently put

28、 into appropriate power modeMemory management&data localityCacheMultiple power states第37页/共54页System Level Power OptimizationEnergy is consumed by all hardware unitsSoftware organization affects hardware energy consumptionManagement:run-time system management and control of all units第38页/共54页Energy

29、Saving PrincipleOnly need to run just fast enough to meet the application software deadlines and maintain qualityRun task as slow as possibleReduce voltage to lower levelRun task in time availableReduce voltage to match timeSource:ARM.IEM:Intellectual Energy Management第39页/共54页Dynamic power manageme

30、ntWhat is Dynamic power management?To selective shutoff or slow-down of system components that are idle or underutilizedPower manager observes system&responds at run-time第40页/共54页Why OS Directed Power Management?第41页/共54页Dynamic Voltage and Frequency ScalingDynamic Power ManagementChange the power s

31、tate of the system components to lower the energy consumption depending on the performance constraintsDynamic Voltage and Frequency Scaling(DVFS)Adjust the performance and energy consumption levels while the device is activeKey is to meet users performance needs while saving energyReduce the process

32、ors voltage and frequency to obtain quadric energy saving第42页/共54页Example A close loop intelligent energy managementIncrease the battery life of handheld portable devices in several stages from 25%up to 400%.DVS&DFS designed by ARM&National Semiconductor ARM&National Semiconductor第43页/共54页News on Ju

33、ly 18,2006:TSMC and ARM Collaboration Achieves Significant Power Reduction On 65nm Low-Power Test ChipPower Management StrategyMulti-corner timing closure capability,which anticipates the timing impact of voltage scaling on the timing of library cells that offer different threshold voltages.This tec

34、hnique recognizes shifts in the critical path and earmarks them for timing analysis at any point in the design cycle.Multi-threshold(MT)CMOS technology is implemented together with dynamic voltage and frequency scaling(DVFS)to reduce dynamic and standby(leakage)power for different operating conditio

35、ns.Design methodologies are demonstrated for power-gating cell wake-up/sleep control,power isolation and timing signoff for voltage islands.ARM Intelligent Energy Manager(IEM)technology supports dynamic voltage and frequency scaling,and is now being extended to include leakage control using power ga

36、ting and state retention under software control.第44页/共54页Summary of Power Reduction TechniqueSource:conference papers,magazine articles低功耗技术漏电功耗的减小静态功耗的减小时序影响面积影响设计方法影响验证复杂度影响仿真影响面积优化10%10%0%-10%无低无多阈值工艺80%0%0%2%低低无时钟门控020%0%2%低低无多电压50%40-50%0%10%中中低电源门控90-98%0%4-8%5-15%中高低动态电压及动态频率缩放 50-70%40-70%0%

37、10%高高高体偏置90%-10%10%高高高第45页/共54页OutlineWhy low powerSources of power consumptionLow power design methodologyLow power techniques Power analysis and toolsTrends in the future第46页/共54页PurposeFind the main power consumption components in our design to help us optimization designFind the power consumptio

38、n in early stage to to enable efficient design space exploration and help system level decisions 第47页/共54页Power Types and UsesPeak powerNeed to size power busses,limit ground noise(bounce)Time averaged powerPackage choicesCooling devices and systemBattery lifeRMS(Root mean square)Used for electromig

39、ration rules第48页/共54页Accuracy vs.Efficiency Tradeoff第49页/共54页Power Estimation and SimulationRTLEarly-analysis,fastest,simulation pattern refining and debugging easierLess accurate,results depend on the accuracy of library data Gate LevelAccurate-analysis,simulation with RC and SDFNeed accuracy libra

40、ry,state dependent leakage power not accurately modeled in librariesTransistor levelVery accurate analysis,accurate leakage measurements.Results dont depend on library,close to silicon measurements,Very late in design phase,long run time第50页/共54页Glance at ToolsAnalysis levelAnalysis ToolNotesRTLPowe

41、rTheater Power Complier(synthesis)Quick RTL power analysis;Power-aware synthesis and gate level optimizationGatePrimePower(simulation)Accurate dynamic power analysis,pattern-dependent modeling of captive switching,short-circuit&static powerTransistorPowerMill(simulation)Transistor-level,pattern depe

42、ndant,high speed,high capacity simulation,with 25%of SPICEPolygonRailMillAstro-RailBlaster-Railvoltage drop and electromigration analysis on power and ground network第51页/共54页Trends in FutureDesign abstract level:More attention will be paid for the higher abstract level power modelLow power design fo

43、r test circuits:Power dissipation under testing condition is 100200%higher than normalTest scheduling;circuit;ATPG with less switching activity etc.Asynchronous circuits:Synchronous circuit:Clock tree is power hungryAsynchronous circuit:no need to balance clockMemory:Memory will occupy more space in chip than Logic,that means memory system are required to perform power reduction第52页/共54页SoC设计方法与实现设计方法与实现郭炜郭炜 郭筝郭筝 谢憬谢憬Thank you第53页/共54页感谢您的观看！第54页/共54页