使用LabVIEW-FPGA模块开发可编程自动化控制器-外文文献及翻译.doc

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1、使用LabVIEW FPGA模块开发可编程自动化控制器学院： 通信与电子工程学院 班级： 电子071 学号： 姓名： Building Programmable Automation Controllers with LabVIEW FPGAOverviewProgrammable Automation Controllers (PACs) are gaining acceptance within the industrial control market as the ideal solution for applications that require highly integrate

2、d analog and digital I/O, floating-point processing, and seamless connectivity to multiple processing nodes. National Instruments offers a variety of PAC solutions powered by one common software development environment, NI LabVIEW. With LabVIEW, you can build custom I/O interfaces for industrial app

3、lications using add-on software, such as the NI LabVIEW FPGA Module. With the LabVIEW FPGA Module and reconfigurable I/O (RIO) hardware, National Instruments delivers an intuitive, accessible solution for incorporating the flexibility and customizability of FPGA technology into industrial PAC system

4、s. You can define the logic embedded in FPGA chips across the family of RIO hardware targets without knowing low-level hardware description languages (HDLs) or board-level hardware design details, as well as quickly define hardware for ultrahigh-speed control, customized timing and synchronization,

5、low-level signal processing, and custom I/O with analog, digital, and counters within a single device. You also can integrate your custom NI RIO hardware with image acquisition and analysis, motion control, and industrial protocols, such as CAN and RS232, to rapidly prototype and implement a complet

6、e PAC system.Table of Contents1. Introduction 2. NI RIO Hardware for PACs 3. Building PACs with LabVIEW and the LabVIEW FPGA Module 4. FPGA Development Flow 5. Using NI SoftMotion to Create Custom Motion Controllers 6. Applications 7. Conclusion Introduction You can use graphical programming in LabV

7、IEW and the LabVIEW FPGA Module to configure the FPGA (field-programmable gate array) on NI RIO devices. RIO technology, the merging of LabVIEW graphical programming with FPGAs on NI RIO hardware, provides a flexible platform for creating sophisticated measurement and control systems that you could

8、previously create only with custom-designed hardware.An FPGA is a chip that consists of many unconfigured logic gates. Unlike the fixed, vendor-defined functionality of an ASIC (application-specific integrated circuit) chip, you can configure and reconfigure the logic on FPGAs for your specific appl

9、ication. FPGAs are used in applications where either the cost of developing and fabricating an ASIC is prohibitive, or the hardware must be reconfigured after being placed into service. The flexible, software-programmable architecture of FPGAs offer benefits such as high-performance execution of cus

10、tom algorithms, precise timing and synchronization, rapid decision making, and simultaneous execution of parallel tasks. Today, FPGAs appear in such devices as instruments, consumer electronics, automobiles, aircraft, copy machines, and application-specific computer hardware. While FPGAs are often u

11、sed in industrial control products, FPGA functionality has not previously been made accessible to industrial control engineers. Defining FPGAs has historically required expertise using HDL programming or complex design tools used more by hardware design engineers than by control engineers.Withinthet

12、est-fixturethetxoutputofthetransmittermoduleisloopedbacktotherxinputofthereceivermodule.Thisallowsthetransmittermoduletobeusedastestsignalgeneratorforthereceivermodule.Datacanbewritteninparallelformattothetransmittermoduleandloopedbackinserialformattotherxinputofthereceivermodule,anddatareceivedcanf

13、inallybereadoutinparallelformatfromthereceivermodule.InordertoautomatethetestingoftheUARTasmuchaspossible,treeindependentVerilogtaskswerewrittenasfollows.TheVerilog task“write_to_transmitter”holdsallnecessarystatementsrequiredtogenerateasingleparalleldatawritesequencetothetransmittermodule.Datathata

14、rewrittentothetransmitteruponexecutionofthe“write_to_transmitter”task,getlatchedinternaltothetest-fixtureforlateranalysis.TheVerilogtask“read_out_receiver”holdsallnecessarystatementsrequiredtogenerateasingle paralleldatareadoutsequencefromthereceivermodule.Datathatarereadoutofthereceiveruponexecutio

15、nofthe“read_out_receiver”task,getlatchedinternaltothetest-fixtureforlateranalysis.TheVerilogtask“compare_data”holdsallnecessarystatementsrequiredtocomparethepreviousdatawrittentothetransmittermodule,to thecorrespondingandmostrecentdatareceivedandreadoutfromthereceivermodule.Ifanydiscrepancyoccurs,th

16、e“compare_data”taskflagsforanerrorbywritingoutthedatavaluesthatwerewrittentothetransmittermodule,aswellasthecorrespondingdatavaluesthatwerereceivedbyandreadoutfromthereceivermodule.Thesimulationisimmediatelystoppedbythe“compare_data”taskifanydiscrepancyoccurs.BesidesthetreeabovementionedVerilogtasks

17、,thetest-fixtureholdsthestatementstogeneratethemclkx16,themasterresetsignalsaswellasthe“txtorx”loopbackfeature.Thestatementsareconsideredtrivial,andwillnotbeillustratedhere,butcanbereferredtowithinthetest-fixtureitself.Thecoreofthetest-fixtureisabehaviorallevel“forloop”thatexecutesthetreeabovementio

18、nedVerilogtasksinordertowriteallpossibledatacombinationstothetransmitterandverifythatsamedatagetsproperlyreceivedbythereceiver.Theforloopisshowed below in figure 21.Nexttoportdefinitionscomesportdirections.Directionsarespecifiedasinput,outputorinout(bidirectional),andcanbereferredtointable1.Nexttoth

19、e specificationofportdirectionscomesdeclarationofinternalsignals.InternalsignalsinVerilogaredeclaredas“wire”or“reg”datatypes.Signalsofthe“wire”typeareusedforcontinuosassignments,alsocalledcombinatorialstatements.Signalsofthe“reg”typeareusedforassignmentswithintheVerilog“always”block,oftenuseforseque

20、ntiallogicassignments,butnotnecessarily.ForfurtherexplanationseeaVerilogreferencebook.Datatypesoftheinternalsignalsofthemodulecanbereferredtointable3.Wehavenowpassedbyallnecessarydeclarations,andarenowreadytolookattheactualimplementation.Usinghardwaredescriptionlanguageallowsusto describethefunction

21、ofthetransmitterinamorebehavioralmanner,ratherthanfocusonitsactualimplementationatgatelevelInsoftwareprogramminglanguage, functionsandproceduresbreakslargerprogramsintomorereadable,manageableandcertainlymaintainablepieces.TheVeriloglanguageprovidesfunctionsandtasksasconstructs,analogoustosoftwarefun

22、ctionsandprocedures.AVerilogfunctionand taskareusedastheequivalenttomultiplelinesofVerilogcode,wherecertaininputsorsignalsaffectscertainoutputsorvariables.Theuseoffunctionsandtasksusuallytakesplacewheremultiplelinesofcodearerepeatedlyusedinadesign,andhencemakesthedesigneasiertoreadandcertainlymainta

23、in.AVerilogfunction canhavemultipleinputs,butalwayshaveonlyoneoutput,whiletheVerilogtaskcanhavebothmultipleinputs,andmultipleoutputsandeveninsomecases,nonofeach.BelowisshowntheVerilogtask,thatholdallnecessarysequentialstatements,todescribethetransmitterinthe“shift”modeWith the LabVIEW FPGA Module an

24、d NI RIO hardware, you now can use LabVIEW, a high-level graphical development environment designed specifically for measurement and control applications, to create PACs that have the customization, flexibility, and high-performance of FPGAs. Because the LabVIEW FPGA Module configures custom circuit

25、ry in hardware, your system can process and generate synchronized analog and digital signals rapidly and deterministically. Figure 1 illustrates many of the NI RIO devices that you can configure using the LabVIEW FPGA Module.Figure 1. LabVIEW FPGA VI Block Diagram and RIO Hardware Platforms NI RIO H

26、ardware for PACs Historically, programming FPGAs has been limited to engineers who have in-depth knowledge of VHDL or other low-level design tools, which require overcoming a very steep learning curve. With the LabVIEW FPGA Module, NI has opened FPGA technology to a broader set of engineers who can

27、now define FPGA logic using LabVIEW graphical development. Measurement and control engineers can focus primarily on their test and control application, where their expertise lies, rather than the low-level semantics of transferring logic into the cells of the chip. The LabVIEW FPGA Module model work

28、s because of the tight integration between the LabVIEW FPGA Module and the commercial off-the-shelf (COTS) hardware architecture of the FPGA and surrounding I/O components.National Instruments PACs provide modular, off-the-shelf platforms for your industrial control applications. With the implementa

29、tion of RIO technology on PCI, PXI, and Compact Vision System platforms and the introduction of RIO-based CompactRIO, engineers now have the benefits of a COTS platform with the high-performance, flexibility, and customization benefits of FPGAs at their disposal to build PACs. National Instruments P

30、CI and PXI R Series plug-in devices provide analog and digital data acquisition and control for high-performance, user-configurable timing and synchronization, as well as onboard decision making on a single device. Using these off-the-shelf devices, you can extend your NI PXI or PCI industrial contr

31、ol system to include high-speed discrete and analog control, custom sensor interfaces, and precise timing and control. NI CompactRIO, a platform centered on RIO technology, provides a small, industrially rugged, modular PAC platform that gives you high-performance I/O and unprecedented flexibility i

32、n system timing. You can use NI CompactRIO to build an embedded system for applications such as in-vehicle data acquisition, mobile NVH testing, and embedded machine control systems. The rugged NI CompactRIO system is industrially rated and certified, and it is designed for greater than 50 g of shoc

33、k at a temperature range of -40 to 70 C.NI Compact Vision System is a rugged machine vision package that withstands the harsh environments common in robotics, automated test, and industrial inspection systems. NI CVS-145x devices offer unprecedented I/O capabilities and network connectivity for dist

34、ributed machine vision applications.NI CVS-145x systems use IEEE 1394 (FireWire) technology, compatible with more than 40 cameras with a wide range of functionality, performance, and price. NI CVS-1455 and NI CVS-1456 devices contain configurable FPGAs so you can implement custom counters, timing, o

35、r motor control in your machine vision application.Building PACs with LabVIEW and the LabVIEW FPGA ModuleWith LabVIEW and the LabVIEW FPGA Module, you add significant flexibility and customization to your industrial control hardware. Because many PACs are already programmed using LabVIEW, programmin

36、g FPGAs with LabVIEW is easy because it uses the same LabVIEW development environment. When you target the FPGA on an NI RIO device, LabVIEW displays only the functions that can be implemented in the FPGA, further easing the use of LabVIEW to program FPGAs. The LabVIEW FPGA Module Functions palette

37、includes typical LabVIEW structures and functions, such as While Loops, For Loops, Case Structures, and Sequence Structures as well as a dedicated set of LabVIEW FPGA-specific functions for math, signal generation and analysis, linear and nonlinear control, comparison logic, array and cluster manipu

38、lation, occurrences, analog and digital I/O, and timing. You can use a combination of these functions to define logic and embed intelligence onto your NI RIO device.Figure 2 shows an FPGA application that implements a PID control algorithm on the NI RIO hardware and a host application on a Windows m

39、achine or an RT target that communicates with the NI RIO hardware. This application reads from analog input 0 (AI0), performs the PID calculation, and outputs the resulting data on analog output 0 (AO0). While the FPGA clock runs at 40 MHz the loop in this example runs much slower because each compo

40、nent takes longer than one-clock cycle to execute. Analog control loops can run on an FPGA at a rate of about 200 kHz. You can specify the clock rate at compile time. This example shows only one PID loop; however, creating additional functionality on the NI RIO device is merely a matter of adding an

41、other While Loop. Unlike traditional PC processors, FPGAs are parallel processors. Adding additional loops to your application does not affect the performance of your PID loop.Figure 2. PID Control Using an Embedded LabVIEW FPGA VI with Corresponding LabVIEW Host VI. FPGA Development Flow After you

42、create the LabVIEW FPGA VI, you compile the code to run on the NI RIO hardware. Depending on the complexity of your code and the specifications of your development system, compile time for an FPGA VI can range from minutes to several hours. To maximize development productivity, with the R Series RIO

43、 devices you can use a bit-accurate emulation mode so you can verify the logic of your design before initiating the compile process. When you target the FPGA Device Emulator, LabVIEW accesses I/O from the device and executes the VI logic on the Windows development computer. In this mode, you can use

44、 the same debugging tools available in LabVIEW for Windows, such as execution highlighting, probes, and breakpoints.Once the LabVIEW FPGA code is compiled, you create a LabVIEW host VI to integrate your NI RIO hardware into the rest of your PAC system. Figure 3 illustrates the development process fo

45、r creating an FPGA application. The host VI uses controls and indicators on the FPGA VI front panel to transfer data between the FPGA on the RIO device and the host processing engine. These front panel objects are represented as data registers within the FPGA. The host computer can be either a PC or

46、 PXI controller running Windows or a PC, PXI controller, Compact Vision System, or CompactRIO controller running a real-time operating system (RTOS). In the above example, we exchange the set point, PID gains, loop rate, AI0, and AO0 data with the LabVIEW host VI.Figure 3. LabVIEW FPGA Development F

47、lowThe NI RIO device driver includes a set of functions to develop a communication interface to the FPGA. The first step in building a host VI is to open a reference to the FPGA VI and RIO device. The Open FPGA VI Reference function, as seen in Figure 2, also downloads and runs the compiled FPGA code during execution. After opening the reference, you re