2022年电气电子专业_外文翻译_外文文献_英文文献_用SPMC75的P.doc

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1、BLDC Motor Speed Estimation Using PDC Timer Module1 Speed Calculation of BLDC 1.1 Summary of BLDCSince current BLDC has substituted the electrical commutator for the mechanical one, it eliminates the disadvantages of noise, spark, electromagnetic disturbance, short lifetime, etc. Now BLDC is provide

2、d with advantages of simple structure, dependable operation and easy maintenance as AC motor does, as well as advantages of high efficient, no excitation cost and functional speed regulation as traditional DC motor does. So it is widely used in various fields of industrial control now.1.2 PDC Module

3、 Introduction SPMC75F2413A provides two channels of 16 bit PDC (Phase Detection Control, PDC) timers used for capture function and PWM operation. It also supports position detection features for Brushless-DC motor application. The PDC timers are very suitable for both mechanical speed calculation, w

4、ith ACI and BLDC motor included, and phase commutation for changing current conduction according to position information. Figure 1-1 shows the block diagram of entire PDC timers, channel 0 and channel 1. For details of PDC timers specification, please refer to Table 1-1.Table 1-1 PDC TimerFunction P

5、DC Timer 0 PDC Timer 1 Clock sources Internal clock: FCK/1, FCK/4, FCK/16, FCK/64, FCK/256, FCK/1024 External clock: TCLKA, TCLKBInternal clock: FCK/1, FCK/4, FCK/16, FCK/64, FCK/256, FCK/1024 External clock: TCLKA, TCLKB IO pins TIO0A, TIO0B, TIO0C TIO1A, TIO1B, TIO1C Timer general register P_TMR0_

6、TGRA, P_TMR0_TGRB, P_TMR0_TGRC P_TMR1_TGRA, P_TMR1_TGRB, P_TMR1_TGRC Timer buffer register P_TMR0_TBRA, P_TMR0_TBRB, P_TMR0_TBRC P_TMR1_TBRA, P_TMR1_TBRB, P_TMR1_TBRC Timer period and counter register P_TMR0_TPR, P_TMR0_TCNT P_TMR1_TPR, P_TMR1_TCNT Capture sample clock Internal clock: FCK/1, FCK/2,

7、FCK/4, FCK/8 Internal clock: FCK/1, FCK/2, FCK/4, FCK/8 Counting edge Count on rising, falling, both edge Count on rising, falling, both edge Counter clear source Cleared on P_TMR0_TGRA, P_TMR0_TGRB, P_TMR0_TGRC capture input. Cleared on P_POS0_DectData position detection data changes. Cleared on P_

8、TMR0_TPR compare matches. Cleared on P_TMR1_TGRA, P_TMR1_TGRB, P_TMR1_TGRC capture input. Cleared on P_POS1_DectData position detection data changes.Cleared on P_TMR1_TPR compare matches. Input capture function Yes Yes PWM compare match output function 1 output Yes Yes 0 output Yes Yes Output Hold Y

9、es Yes Edge-aligned PWM Yes Yes Center-aligned PWM Yes Yes Phase counting mode Yes, phase inputs are TCLKA/TCLKB Yes, phase inputs are TCLK C/TCLKD Timer buffer operation Yes Yes AD convert start trigger P_TMR0_TGRA compare match P_TMR1_TGRA compare matchInterrupt sources Timer 0 TPR interrupt Timer

10、 0 TGRA interrupt Timer 0 TGRB interrupt Timer 0 TGRC interrupt Timer 0 PDC interrupt Timer 0 overflow interrupt Timer 0 underflow interrupt Timer 1 TPR interrupt Timer 1 TGRA interrupt Timer 1 TGRB interrupt Timer 1 TGRC interrupt Timer 1 PDC interrupt Timer 1 overflow interrupt Timer 1 underflow i

11、nterrupt Figure 1-1 PDC Timers Block Diagram 1.3 PDC Operation This note mainly depicts PDC application in motor speed measurement. For detailed PDC introduction, please refer to “SPMC75F2413A Programming Guide” authored by Sunplus. PDC module has four types of registers to perform speed measurement

12、: Timer control register P_TMRx_Ctrl (x = 0, 1), position detection control register P_POSx_DectCtrl (x = 0, 1), input output control register P_TMRx_IOCtrl (x = 0, 1), and timer interrupt enable register P_TMRx_INT (x = 0, 1). Where, P_TMRx_Ctrl and P_POSx_DectCtrl are introduced in detail. 1.31Inp

13、ut Output Control Register P_TMRx_Ctrl(x = 0, 1) B15 B14 B13 B12B11 B10 B9 B8 R/W R/WR/WR/WR/WR/WR/WR/W 0 0 0 0 0 0 0 0 SPCK MODE CLEGS B7 B6 B5 B4 B3 B2 B1 B0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 SPCK MODE CLEGSBit 15:14 SPCK: Capture input sample clock select. These bits select the capt

14、ure input sample clock. Capture input will be sampled with sample clock. Pulses shorter than four sample clocks will be considered invalid, and will be ignored.00 = FCK/1 01 = FCK/210 = FCK/4 11 = FCK/8Bit 13:10 MODE: Modes select. These bits are used to select the timer operation modes. 0000 = Norm

15、al operation (continuous counter up counting) 0100 = Phase counting mode 1 0101 = Phase counting mode 2 0110 = Phase counting mode 3 0111 = Phase counting mode 4 1x0x = Edge-aligned PWM mode (continuous counter up counting, PWM output) 1x1x = Center-aligned PWM mode (continuous counter up/down count

16、ing, PWM output)Bit 9:8 CLEGS: Counter clear edge select. These bits select the counter clearing edge when the clearing source is in input capture mode.00 = do not clear 01 = rising edge 10 = falling edge 11 = both edgeBit 7:5 CCLS: Counter clear source select. These bits select the TCNT counter cle

17、aring source. 000 = TCNT clearing disabled 001 = TCNT cleared by P_TMRx_TGRA (x = 0, 1) capture input 010 = TCNT cleared by P_TMRx_TGRB (x = 0, 1) capture input 011 = TCNT cleared by P_TMRx_TGRC (x = 0, 1) capture input 100 = TCNT cleared by every P_POSx_DectData (x = 0, 1) change 6 times101 = TCNT

18、cleared by every P_POSx_DectData (x = 0, 1) change 3 times 110 = TCNT cleared by P_POSx_DectData (x = 0, 1) position detection data change 111 = TCNT cleared by P_TMRx_TPR (x = 0, 1) compare matchBit 4:3 CKEGS: Clock edge select, These bits select the input clock edge. When the input clock is counte

19、d using both edges, the input clock period is halved. When FCK/1 is selected as counter clock, counter will count at rising edge if count at both edges is selected.00 = Count at rising edge 01 = Count at falling edge 1X = Count at both edgesBit 2:0 TMRPS: Timer pre-scalar select. These bits select t

20、he TCNT counter clock source. It can be selected independently for each channel.000 = Counts on FCK /1 001 = Counts on FCK /4 010 = Counts on FCK /16 011 = Counts on FCK /64 100 = Counts on FCK /256 101 = Counts on FCK /1024 110 = Counts on TCLKA pin input 111 = Counts on TCLKB pin inputControl regi

21、ster configuration P_TMRx_Ctrl(x = 0, 1) is used for the selection of input capture during speed measurement. Rather than being a general input signal, the input capture is a period between two position detection changes triggered by PDC interrupt. This period must be counted with a certain frequenc

22、y supported by a clock source. Thus, the counters on this function must be configured. MODE: Select a timer operation mode in seven modes. However, only the normal operation (continuous counter up counting) mode can be selected in this application, because the other six modes are all related to phas

23、e counting mode or PWM mode. CCLS: Select a TCNT counter clearing source from eight settings. In this application, one among the three can be set: 100, 101 or 110, which respectively indicates that TCNT is cleared for once every 6/3/1 times P_the POSx_DectData (x = 0, 1) changes. Also, they can be d

24、escribed as: TCNT is cleared for once every 360/180/60 electrical degree rotation of BLDC. This setting is critical for converting electrical revolution to mechanical revolution and measuring the BLDC speed.CKEGS: Select the input clock edge, which can be rising, falling or both edges. When the inpu

25、t clock is counted using both edges, the input clock period is halved. Note to count this factor on during the BLDC speed calculation. TMRPS: Select the TCNT counter clock source from eight settings. This setting determines the precision and the range during BLDC speed measurement. See the example c

26、ode below: P_TMR0_Ctrl, B.MODE = 0; / Normal Counting mode P_TMR0_Ctrl, B.CCLS = 6; / TCNT cleared by P_POSx_DectData (x = 0, 1) / Each time position detection data change P_TMR0_Ctrl, B.CKEGS = 0; / Counting at rising edge P_TMR0_Ctrl, B.TMRPS = 3; / Select FCK/64 clock source 1.3.2 Position Detect

27、ion Control Register P_POSx_DectCtrl(x = 0, 1) B15 B14 B13 B12B11 B10 B9 B8 R/W R/WR/WR/WR/WR/WR/WR/W 0 0 0 0 0 0 0 0 SPLCK SPLMOD SPLCNT B7 B6 B5 B4 B3 B2 B1 B0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0PDEN SPDLYBit 15:14 SPLCK: Sampling clock select. Select FCK/4, FCK/8, FCK/32, or FCK/128 f

28、or position sampling clock 00 = FCK/4 01 = FCK/8 10 = FCK/32 11 = FCK/128Bit 13:12SPLMOD: Sampling mode select. Select one of three modes: sampling when PWM signal is active (PWM is on), sampling regularly, or sampling when lower side (UN, VN, WN) phases are conducting current. 00 = Sample when UPWM

29、/VPWM/WPWM bit is set in P_TMRx_OutputCtrl (x = 3, 4) register and generate the PWM waveform01 = Sample regularly 10 = Sample when lower phases is in active state and conducting current 11 = ReservedBit 11:8SPLCNT: Sampling count select. These bits select the sampling count for the valid external po

30、sition detection signals. The position signals must be sampled continuously match as many times as the sampling count set, for the position signals to be considered valid. The valid settings are from 1 to 15 times. Note that count 0 and 1 are assumed to be one time.Bit : 7PDEN: Position detection en

31、able. This bit enables/disables the position detection function for position input pins TIOAC. When enabled, the input signals of these pins will be sampled and the results will be latched to PDR 2:0 bits in POS_DectData register. When disabled, PDR 2:0 will remain its status. 0 = Disable 1 = Enable

32、Bit 6:0SPDLY: Sampling delay. These bits set a delay time clock in which at SPLCK clock source. It is used to stop sampling in order to prevent erroneous detection due to noise that occurs immediately after PWM output turns on.Position detection control register When the position detection changing

33、event occurs, the P_TMRx_TCNT (x = 0, 1) value can be transferred to TGRA. If the position detection interrupt enable bit PDCIE is set to 1 in the corresponding P_TMRx_INT (x = 0, 1) register, the PDC interrupt routine will be called to process the data. SPLCK: Select sampling clock from FCK/4, FCK/

34、8, FCK/32, or FCK/128 for position sampling clock, which determines the detection precision of position change. Proper setting of SPLCK, SPLCNT and SPDLY will help to prevent erroneous detection and filter the disturbance. SPLMOD: Select one of these three modes: sampling when PWM signal is active (

35、PWM is on), sampling regularly, or sampling when lower side (UN, VN, WN) phases are conducting current. SPLCNT: Sampling count select. The valid settings are from 1 to 15 times. Note that count 0 and 1 are both assumed to be one time. PDEN: This bit enables/disables the position detection function f

36、or position input pins TIOAC. SPDLY: Sampling delay with the range of 0 to 127.The setting example is shown as blew. P_POS0_DectCtrl, B.SPLCK = 2; / Count on FCK/32 P_POS0_DectCtrl, B.SPLMOD = 1; / Sample regularly P_POS0_DectCtrl, B.SPLCNT = 10; / Sample 10 times P_POS0_DectCtrl, B.PDEN = 1; / Enab

37、le position detectionP_POS0_DectCtrl, B.SPDLY = 100; / Sample Delay1.4 Speed CalculationIn order to obtain the exact parameters, the data must be filtered after captured. There are many filter algorithms, such as low-pass filter, moving average filter, median filter, average filter, limiting filteri

38、ng, first-order filter, moving average filtering, etc. In general, the data can be considered valid after processed by these filters. Then the speed can be calculated by substituting these parameters data in the formula. Assume Fcap is PDC capture clock frequency; p is the pole-pair of BLDC rotor; T

39、CNT is cleared every m P_POSx_DectData (x = 0, 1) changes, that is, TCNT is cleared at every rad rotation (m=1, 3, 6), and the position data is NcapSince: (Formula 1- 1)and =, Since electrical degree = p x mechanical rotation then the mechanical angular velocity is (Formula 1- 2)with the unit of rad

40、/min. Take n as the indicator. So: rad/min (Formula 1- 3) n summarize: rpm (Formula 1- 4) From the formula above, we can obverse that n is related to Fcap, m, Ncap and p (that is a constant when BLDC is selected) .Suppose there is a BLDC with 2 pole-pair, 4000rpm rated speed. We will show you how to

41、 set the parameters of Fcap and m. When m= 1, TCNT is cleared every time P_POSx_DectData (x = 0, 1) changes, , that is, TCNT is cleared for once every 60 electrical degree rotation of BLDC. With a certain clock frequency, the motor rotation speed can be calculated by the Formula 1- 4 at the highest

42、speed when Ncap is 1 and the lowest speed when Ncap is 0xffff. Table 1-2 Motor Speed VS Clock FrequencyFcapn FCK/1 FCK/4 FCK/16 FCK/64 FCK/256 FCK/1024Nmax (rpm) 120M 30M 7.5M 1875K 468750 117187.5 Nmin (rpm) 1831 457.8 114.4 28.6 7.2 1.8 When m= 3, TCNT is cleared for once every 3 times P_POSx_Dect

43、Data (x = 0, 1) changes, that is, TCNT is cleared every 180 electrical degree rotation of BLDC. From the Formula 1- 4, we can see that the measurable motor speed when m= 3 is three times higher than that when m= 1, provided that other parameters are the same. When m= 6, TCNT is cleared every 6 times

44、 P_POSx_DectData (x = 0, 1) changes, that is, TCNT is cleared every 360 electrical degree rotation of BLDC.From the Formula 1- 4, we can see that the measurable motor speed when m= 6 is six times higher than that when m= 1, provides that other parameters are the same. Above all, it is better to set

45、m= 1 to ensure the veracity of positions. Since the highest speed can be applied, it is important to select the lowest speed. Assume the lowest measure speed is 200 rpm, we can set Fcap as FCK/16, FCK/64, FCK/256 or FCK/1024. FCK/16 is recommended to be selected for higher veracity.1.5 Noise Immunit

46、y Through programming the bit value of SPLCNT (sampling count select) and SPDLY (sampling delay) in P_POSx_DectCtrl(x = 0, 1), users could avoid the erroneous detection due to noise that occurs immediately after PWM output turns on. It can ensure the correctness of speed measurement and phase commutation in BLDC . The v