全新架构的全数位式无类比锁相倍频电路Create DLL circuit.ppt

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1、全新架構的全數位式無類比鎖相倍頻電路Create DLL circuit and Multiple frequency with VHDL or VERILOG in CPLD,FPGA or ASIC 授課教授授課教授:陳永耀陳永耀 博士博士 學生學生:藍浩濤藍浩濤 P90921001P90921001 電機所控制組電機所控制組 OUTLINEn nAbstractn nPurposes of DLLn nDLL Definition and Principlen nCircuit Design with VHDL in CPLD and FPGA Flowchartn nSimulatio

2、n Wave for Lattice CPLDn nExperimental Results on Oscilloscopen nConclusionsAbstract DLL usually implements with logic and analog circuit in ASIC design.CPLD and FPGA are logic devices,and must design DLL or PLL to implement in devices design first.Could we create a simple DLL circuit with VHDL or V

3、erilog implementing in CPLD,FPGA or ASIC?Purposes of DLLADC and DACCPU designSingle chip designSOC designDDR designWireless circuitDSPDLL definition and principleDLL(Delay Lock Loop)Circuit design with VHDL in CPLD and FPGA Flowchart LanguageDescriptionRTL(Register Transfer Level)Transfer to RTL for

4、matCell MappingOptimal circuitNetlist of circuitAuto Compiler Flow in CPLD and FPGASimulation Waves for Lattice CPLDn nLattice 2032VE-110 n nLattice 2064VE-100 n nLattice M4A3-256/100n nAltera EPM7032LC44-6Lattice 2032VE-110 Lattice 2032VE-110 Lattice 2064VE-100 Lattice M4A3-256/100 Altera EPM7032LC

5、44-6 Experimental Results on OscilloscopeLattice M4A3-256/160-10YC 及電路板實際外觀 Lattice 2064VE-100LT100 及電路板實際外觀 Lattice M4A3-256/160-10YC 延遲的輸出波形 Lattice M4A3-256/160-10YC 倍頻的輸出波形 Lattice 2064VE-100LT100 鎖相的輸出波形 Lattice 2064VE-100LT100 鎖相的輸出波形 Lattice 2064VE-100LT100 延遲的輸出波形 Lattice 2064VE-100LT100 鎖相的

6、輸出波形 Lattice 2064VE-100LT100 鎖相的輸出波形 Lattice 2064VE-100LT100 倍頻的輸出波形 Lattice 2064VE-100LT100 延遲的輸出波形 儀器誤差+電路板誤差+測試棒誤差+測試棒接點電阻延遲誤差+電路板RC延遲誤差=900ps Conclusionsn n鎖相只需一個鎖相只需一個 延遲時間延遲時間(only one only one locking time)locking time)n n只有靜態耗電，沒有動態耗電只有靜態耗電，沒有動態耗電 n n可輕易的實現於可輕易的實現於CPLDCPLD，FPGAFPGA，ASIC ASIC n nFully IP Fully IP n n無無JitterJittern n完全沒有類比電路，也不需要完全沒有類比電路，也不需要ICIC外部的電阻電外部的電阻電容或者是電感容或者是電感 n n無無VCO VCO 內部震盪器內部震盪器