Quartus II And FPGA Design Flow.ppt

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1、Quartus II And FPGA Design FlowAgendanQuartus II setup and LicensenQuartus II SetupnLicense SettingnFPGA Design FlownDesign Entry 设计输入nSynthesis 综合nPlace and Routing 布局布线nVerification验证 n Device Programmer 编程nTesting 调试 Quartus II setup and License SettingnQuartus II setupnWindows 2000:点击安装文件安装，安装后要

2、在软件中设置License的路径nWindows XP：点击安装文件安装，安装完成后需要在软件中设置license的路径n说明：用户可以根据自己的需要，增加安装相关第三方或者Altera提供的软件，例如Synplify，Modelsim，NIOS II等License Settingn为了正常使用为了正常使用Quartus II，安装完毕后需要对，安装完毕后需要对License进进行正确的设置。行正确的设置。n设置方法：打开设置方法：打开Quartus II软件，点击下拉菜单软件，点击下拉菜单Tools，在弹出的菜单中选择在弹出的菜单中选择License Setup。License Setti

3、ngn在弹出的对话框中选择在弹出的对话框中选择License的存放路径，设置完毕后的存放路径，设置完毕后点击点击OK即可。即可。FPGA Design FlowDesign EntrySynthesisPlace & RouteSimulationTiming AnalysisProgramming & ConfigurationDebuggingPower AnalysisEngineering change ManagementTiming ClosurePowerPlay Analyzer ToolPowerPlay Early Power EstimatorSignalTap II,

4、SignalProbe, Insystem Memory Content Editor, RTL Viewer, Technology Map Viewer, Chip EditorChip Editor, Resource property Editor, Change ManagerFloorPlan Editor, Logiclock Window, Timing Optimization Advisor, Design Space ExplorerFPGA Design FlownRequirement analysisnSummary DesignnDetail Design sho

5、uld RTL levelnCoding (Coding Style)nSimulation nTiming analysisnTestingAttention:Should adopt Top-Down flowModule DesignFPGA Design Flow in Quartus IInDesign Entry 设计输入nSynthesis 综合nPlace and Route 布局布线nSimulation 仿真 nTiming AnalysisnProgramming & Configuration编程nTesting 调试 Design Entry 设计输入nText Ed

6、itorVHDLVerilog （Recommendation）AHDLMultiple InputnBlock & Symbol EditornMegawizard Plug-in Manager (Same as Xilinx Core generate)nAssignment Editor & Pin planner (New in Quartus5.0)nFloorplan EditorSynthesis 综合nAnalysis & SynthesisnVHDL, Verilog & AHDLDo what you like and company main design langua

7、geLittle difference nDesign AssistantnRTL ViewernTechnology Map ViewernIncremental Systhesis (Easy to use and high performance especially efficiency for complicated design)Place & RoutenFitternAssignment Editor & Pin Planner (New in Quartus II5.0)nFloorplan EditornReport Window (Should care about me

8、ssage in this window and be sure about must no Error and fatal warning.)nResource Optimization AdvisornDesign Space ExplorerSimulationnSimulatornWaveform EditornSimulation toolsModelSimSimulate tools embed in QuartusNCsimOther simulation tool Etc Attention: This Step is very important in design fllo

9、w! Dont bypass this step please.Timing AnalysisnTiming AnalyzernReport WindownTechnology Map ViewerThis step based on Simulation result.ProgrammingnProgramming Device for TestingnSelect download mode, Such as AS, PS,FPP EtcnSelect appropriate download cableTestingnAfter Complete Design include Timin

10、g analysis can start testingnExperience is important to solve questionnReserve test pin is the bestnUse SignalTap II Logic analyzernUse oscillographnUse Logic analysis equipment (If need)nOther meansSummarynQuartus II setup and LicensenQuartus II SetupnLicense SettingnFPGA Design FlownDesign Entry 设计输入nSynthesis 综合nPlace and Routing 布局布线nVerification验证 n Device Programmer 编程nTesting 调试 Any Question?nAltera today?nQuartus II Setup?nSoftware ?nDevices ?nVHDL & Verilog ?nOther ?The EndThank youFrank Wang 2005/08/15Cytech WH Office FAEMP:13396085303Email: