clock Application Notes.ppt

《clock Application Notes.ppt》由会员分享，可在线阅读，更多相关《clock Application Notes.ppt（56页珍藏版）》请在得力文库 - 分享文档赚钱的网站上搜索。

1、IDT Clock Application and Programming Guide2005 Aug. By T.W.時鐘的重要性時鐘的重要性程序执行的节拍控制和系统的工作速度由时钟决定硬件设计的基础寄存器级传送和有限状态机（内部时序控制电路）都离不开时钟 。芯片间接口数据的发送与接受要以时钟为参考系统的稳定性与时钟有密切关系Clock Distribution96 MHzCK_33M_1394CK_33M_SL1K Ke ey yb bo oa ar rd dI In nt te el lP Pr re es sc co ot tt t33 MHzCK_14M_ICHP PC CI I1

2、1 S Sl lo ot tRBITCLKG GM MC CH HCK_100M_ICH/#P PC CI I3 3 S Sl lo ot tO On n B Bo oa ar rd dP PC CI I2 2 S Sl lo ot tM Mo ou us se e100 MHz24 MHz33 MHz100 MHzI IC CH H6 648 MHzCK_33M_FWHI IE EE EE E 1 13 39 94 4200 MHzMHzA AG GE ER RE E M MO OD DE EN NM_CHA_CLK0.2/#I IN NT TE EL L P PH HY Y8 82 25

3、56 62 2G GT TCK_96M_DREF/#CK_48M_USBF FW WH HCK_33M_LANI IC CS S9 95 54 45 55 53 333 MHz33 MHzC Co od de ec cCK_33M_ICHD DD DR RI I 1 133 MHzCK_33M_SIOCK_24.5M_1394100 MHz33 MHzKB_CLKI In nt te el l P Pr ro oc ce es ss so or rG Gr ra an nt ts sd da al le eD DD DR RI I 2 2CK_33M_SL333 MHzA A8 80 00 0

4、0 0CK_25M_LANCPUHCLK/#C CL LO OC CK K C CH HI IP PCK_33M_SL2200MHzCK_100M_MCH/#14.318 MHz7 77 75 5 P Pi in n P Pa ac ck ka ag ge eM_CHB_CLK0.2/#CK_100M_SATA/#MSE_CLKA AZ ZA AL LI IA AI In nt te el lCK_14M_SIO14.318 MHzMCHHCLK/#33 MHzHOST 200MHZCPUHCLKMCHHCLKSRC Clocks (100MHz Differential Clocks for

5、 Serial Reference Clocks)NB_ALINK_CLK/NB_ALINK_CLK#REFCLK/REFCLK#_x16REFCLK/REFCLK#_x1NB_PCIE_CLK/ NB_PCIE_CLK#SB_ALINK_CLK/SB_ALINK_CLK#48MHz CLOCK CK_48M_ICH 33MHz CLOCK PCI_CK_33M_ICHPCI_CK_33M_SIOPCI_CK_33M_FWHPCI_CK_33M_LANPCI_CK_33M_SLT1PCI_CK_33M_SLT214MHz CLOCKnCK_14M_ICHnCK_14M_SIOAC97/AZAL

6、IA CLOCK nAZALIA_BIT_CLK OTHER CLOCK nSUSCLKn25MHz XTAL-IN(LAN)DDR 400 CLOCK nM_CHA_SCK0, M_CHA_SCK0#nM_CHA_SCK1, M_CHA_SCK1#nM_CHA_SCK2, M_CHA_SCK2#nM_CHB_SCK0, M_CHB_SCK0#nM_CHB_SCK1, M_CHB_SCK1#nM_CHB_SCK2, M_CHB_SCK2# IDT/ICS websitehttp:/http:/Agenda 1:ICS clock part number and data sheet over

7、view 2:ICS clock block Diagram 3:PLL concept:Phase detect, Charge Pump, VCO 4:PLL with M/N divider 5:Skew, Jitter 6:Spread Spectrum: Down Spread, Center Spread 7:Power On latch 8:CK505 9:Xtal capacitor calculation 10:Clock Buffer 11: Real Time Frequency Selection (RTFS) 12:Watch Dog Timer (ratio cha

8、nge/ over clock) 13:Design notes: impedance, placement 14:Product Update 15:Thank youA Global Force in Semiconductor SolutionsShanghaiSan JoseHeadquartersAtlanta,GAOttawaHillsboro,ORPenangSingaporeDesign Engineering CenterWafer Fabrication FacilityAssembly/TestWorcester,MATempe,AZAuburn,NYICS CK505

9、(Low Power) part number Part# rule 9LPXXX/ 9LPRXXX / 9LPRSXXX /LP :Low Power /R :Integrated Regulator /S :Integrated Serial resistor /xxx :Serial Number For example:9LP505-2HFLF9LPR501HFLF9LPRS552AGLFordering information:ICS9LPRSXXX yFLF-Ty: revision, A,B,CG:TSSOP or F: SSOP packageor K:QFNLF: lead

10、free T: tape and reel packagefor example:ICS9LP505-2HFLF-TIDT part number Part# rule CVXXX /xxx : serial number for example:CV174Cordering information:IDTCVxxxYYG8YY :Package PA:TSSOP or PV: SSOP G: Green Part 8: tape and reel package Die revision : (Not with P/N)for example:IDTCV174CPVG8Data Sheet

11、Overview Internal configuration resister pull high/low (H:*/L:*) information 2X driver strength () Revision date information In the lower left corner of page quick Frequency table See byte0 full tableBlock DiagramPLL Concept PLL means ( ) ?VCO = Ref_in Frequency after PLL lockedPhase DetectorVCORef_

12、inVCO Feed BackVCO outputIn phasePhase Lock LoopV_inF_outVCODivider( N )VCODivider( 10)VCODivider( 100)How to get multiple of REF frequency part 1 REF Input14.318MHzPhase DetectorVCO &SpreadModulatorVCO output143.18MHz(REF x 10)14.318MHzVCO output1431.8MHz(REF x 100)After PLL circuit is locked, Phas

13、e detect REF & VCO feedback inputs are in same phase/frequency Ref Input = FB_In = VCO output / DividerIn other wordsVCO output = Ref input * DividerCPUDividerPCIEXDividerZCLKDivider3V66DividerPCIDividerZCLK 3133.33MHz146.66MHzCPU 2200MHz220MHzGet any VCO frequency by controlling the value of M and

14、N dividersVCODivider( N)REF Input14.318MHzREFDivider( M) Phase DetectorVCO &SpreadModulatorHow to get multiple of REF frequency part 2A=REF/M = B=VCO/NA=B = REF/M=VCO/NVCO = N x REF / MAB16x 14.31818MHz447400MHz VCO =VCODivider( 447)REFDivider( 16)PCIEX 4100MHz3V66 666.67MHzPCI 1233.33MHz491440MHz V

15、CO =VCODivider( 491)110MHz73.34MHz36.66MHz10% OVER CLOCK13-14CPUDivPCIEXDivLAN CLKDiv3V66DivPCIDivFrequency ProgrammingnProgrammable ClockVCODivider( N)REF Input14.318MHzREFDivider( M)Phase DetectorVCO &SpreadModulatorH/W, IIC, FS selection control bitRom11 12M/N ValuesI2CSpread %MN control bit will

16、 enable these muxes to pass registers setting by I2CRead BackLatchesSMBUS interfaceHardware FS InputsByte0WD safe frequency(ROM table)00001FS4FS3FS2FS1FS0MM N NSS%NSS%MSS%Jitter, skewTransition too earlyTransition too lateIdeal waveformJitterSkewWhy skew adjustment is very helpful?Change skew by ske

17、w control register Down Spread and Center Spread100.25MhzEffects of Spread Spectrum = 10 dBm199.223 MHz199.97 MHz = .4%Fundamental FrequencyDown spread example 0.4%Spread SpectrumModulation Rate: Current devices use a fixed modulation rate of 33 kHz. This modulation is in a smooth frequency transiti

18、on up to the maximum point and then a smooth transition down to a minimum point. This forms a triangular wave form of frequency vs. time and provides the best dispersion of energy. For 200MHz, the 33kHz modulation frequency with +0.5% modulation has less than 0.00825 ps-per-cycle average modulation

19、slope (rate of change ).200Mhz/33Khz=6060 cycles (3030 cycle up and 3030 cycle down)5ns period x 0.5% spread = 25ps25ps / 3030 cycles = 0.00825ps Frequency latch configuration and timing Please dont connect Multifunction pins to PCI/AGP slots Dont rely on clock chip internal configuration resister,

20、please always add external resister Power On LatchVddFS0 / REF multi function pinFS0 external pull up to VddVttPrwGd transitionFS0 latchingREF clock output 2msCK505CK410 reviewIntel CK410 scheme - current mode clocks to Grantsdale, Lakeport chipset Flexible outputs swing control Always 14mA power co

21、nsumption for each differential outputs pairs Clock chip total power consumption is around 350mA External pull low 50 ohms resisters required9545xxWhats new from CK505CK410CK505Intel CK505 standard scheme All differential outputs regulated form same source External transistor required Very good bypa

22、ssing is needed due to power noise from different frequencies groups Clock chip total power consumption is around 170mA, 50% lower from CK4109LP501-1 (64pin) or 9LP505-2 (56pin)CV173 (64pin) or CV174 (56pin)IDT enhanced CK505 scheme regulator integrated9LPRxxxIDT enhanced CK505 scheme regulator inte

23、grated9LPRxxx : ICS 9LPR501, ICS 9LPR502, IDT CV175IDT enhanced CK505 scheme series resister integrated9LPRSxxx : 9LPRS552 (P2P with 954552) Reduced external bypass caps No external transistor required Regulators for each outputs group. no high frequency noise coupling Clock chip total power consump

24、tion is around 170mA only Channel features supports25MhzRODDOCRLATCHFast S3 resumeTRMODECK505 vs CK410M ComparisonCK505 clock features:1.0.8V low power push-pull mode differential clock pairs2.Vtt_PwrGd/PD# polarity3.Intentional PCI clock to clock 1ns delay4.Fast slew rate 2.58V/ns (37.5120ps with 3

25、00mV window)5.Clock power consumption max. 250mA6.iAMT modeCK410M clock features:1.0.7V current mode differential clock pairs2.Vtt_PwrGd#/PD polarity3.PCI group skew max. 500ps4.175700ps slew rate5.Clock power consumption max. 400mAXtal capacitor selectionAccording to Intel CK410/505 clock specifica

26、tion,ICS CK410/505 clocks internal capacitance is 5pf,(It is different to previous clock spec. 36pf )Therefore you have to use low CL of Crystal, Intel recommended CL is 20pf and Crystal external trim capacitor will be 33pf.Formula: Ce=2*CL-(Cs+Ci)if Crystal CL=32pf then external caps Ce=2*32pf-(2pf

27、+5pf) = 64-7 = 57pf Below are measurement results. Please use a counter to measure clock REF pin. The accuracy ppm= (REF-14.31818)/14.31818*1,000,000. IDT has new technology on PLL to make the Accuracy of clock output less than 1ppm.Buffer (fan out/Zero delay/Programmable)Zero Delay Buffer clockFan

28、out Buffer clockSke wProgrammable SkewIn phaseProgrammable Buffer clockZero Delay Buffer skew adjustmentZero DelayAheadDelayReal Time Frequency Select*FS1/REF0195xxxx48VDDA*FS0/REF1247GNDVDDREF346IREFX1445CPUCLKT_ITPX2544CPUCLKC_ITPGND643GND*FS2/PCICLK_F0742CPUCLKT1*FS4/PCICLK_F1841CPUCLKC1PCICLK_F2

29、940VDDCPUVDDPCI1039CPUCLKT0GND1138CPUCLKC0*MODE/PCICLK01237GNDPCICLK11336SRCCLKTPCICLK21435SRCCLKCPCICLK31534VDDVDDPCI1633Vtt_Pwrgd#GND1732SDATAPCICLK41831SCLKRTFS#19303V66_0/(Reset#)PD#20293V66_1*Sel24_48#/24_48MHz2128GND*FS3/48MHz2227VDD3V66GND23263V66_2VDD4824253V66_3/VCH_CLKReal Time Frequency s

30、witchingH/W latch table frequencyturbo mode H/W latch table frequency100.99Mhz100.99Mhz105Mhz80001000100.9990001001201.99100001010134.66110001011168.41120001100114.99130001101229.99140001110153.32150001111191.64240011000105.00250011001210.00260011010140.00270011011175.00280011100109.99290011101219.9

31、8300011110146.65310011111183.3510% OvrClk No Sp 0.35% CenterSpread15% OvrClk No Sp5% OvrClk No SpRTFS pin is highRTFS pin is lowRTFS pin is highLinear Frequency TableSupported Excel file for very detailed VCO and Spread programming tableDetermining correct series resister valuePlacement consideratio

32、n Far away PWM Far away Chock Far away Power MOSFET Far away power connectorPlacementsExperiment: modify trace pathResult of new traceXtal Layout Topology and Routing Please have single Via for Ce and REF GND.DC R 0.1-0.3 ohmsImpedance 100-300ohm 100MHzRecommended Power Delivery3.3VAnalogPCIREFFB2CP

33、USRC3.3VFB12.2R1R30.047uF110uFCeramic2.2R2USB10uFCeramic10uFCeramic10uFCeramic0.047uF0.047uF0.047uF0.047uF0.047uFVddVssVssFloodLayer 1Good Decoupling Capacitor RoutingVssFloodLayer 1Bad decoupling Capacitor RoutingDecoupling Capacitor RoutingIntel/IDT Desktop Chipsets/Clocks RoadmapClock SolnsChanne

34、l954123OEM954119/CV115CK410 YC954101Clock SolnsChannel954550OEM954119/CV115CK410 YC954101Clock SolnsChannel9LPRS552OEM9LPR501/5029LPRS502/502CV175CK505 YC9LP505-1 (64p)9LP505-2 (56p)CV163 (64p)CV174 (56p)Clock SolnsChannel952647OEM/YC952601Clock SolnsYC = CK505 ?PCIe = gen2 ? Previous Gen Current Ge

35、n Next GenATI Chipset NomenclatureClock Chip Impact: Basic systems have 2 ATIG clocks 1 for GPU, 1 for GPU memory interface, SRC clocks may be used if no over-clocking is needed Some systems have 3 ATIG clocks 2 for GPUs + 1 for shared GPU memory interface Today, top of the line RD Crossfire systems

36、 have 4 ATIG clocks 2 for GPUs + 2 for dedicated GPU memory interfaces Future systems will have upto 6 ATIG clocks 7xx seriesCPU VendorSegmentFamilyGraphics CharacteristicChipsetAMDPerformanceRDxxxCrossFire (Dual Graphics Card)RD480, RD580, RD690Main StreamRSxxxWith On Board GraphicsRS480, RS485RXxx

37、xGraphics Card RequiredRX480IntelPerformanceRDxxxCrossFire (Dual Graphics Card)RD400, RD600Main StreamRSxxxWith On Board GraphicsRS400. RS600ValueRCxxxWith On Board Graphics - ValueRC410ATI/IDT Desktop Chipsets/Clocks (AMD)CPUFamilyDeviceLow Power DeviceDescriptionAMDRD480951422951446 3 ATIG clocks

38、for dual graphics 2 ATIG clocks with Reset-IN functionRS480/485951416 ProgrammableRX480951412CV137 56-pin Reference Design 56-pin Reference DesignRD580951446 56-pin Reference DesignRD690951462951464CV1669LPR142 Low Power Part - 64pin - 4 ATIG Ref Design - 64pin - 4 ATIG 56-pin version - 2 ATIG Low P

39、ower w/ channel over-clockingGreyhound outputs compliant9LPR4629LPR464 Low Power - 64pin/4 ATIG w/ o-c Low Power - 56pin/2 ATIG w/ o-cATI/IDT Desktop Chipsets/Clocks (Intel)CPUFamilyDeviceLow Power DeviceDescriptionIntelRD400951421 3 ATIG clocks for dual graphicsRS400951413 ProgrammableRC410951411CV

40、136951417 56-pin Reference Design 56-pin Reference Design Used on Intel MotherboardsRS600951461951463CV1659LPR1419LPR4619LPR463 Low Power Part - 64pin - 4 ATIG Ref Design - 64pin - 4 ATIG 56-pin version - 2 ATIG Low Power w/ channel over-clockingLow Power - 64pin/4 ATIG w/ o-c Low Power - 56pin/2 AT

41、IG w/ o-cATI/IDT SB600 compliant clocks SB600 has tighter jitter specs on the 14.318MHz REF and the 48MHz clock 14.318MHz is 300 ps cycle-to-cycle 48MHz is 130ps cycle-to-cycleDeviceRevAvailability951412BNow951418CNow951461/3BNow951462/4ANowIDTs VIA Chipsets clock solutionsPT900Reference design solu

42、tions 953002 + 9P946Low power solutions 9LPR701 (64pin), 9LPR702 (56pin)Low power w/ ref design pin out 9LPR730. Sample 9/06P4M900 / PX890Reference design solutions 953002 + 9P936/9P956Integrated DDR solutions 9LPR700 (64pin)K8X890/900Reference design solutions 953201Low power solutions 9LPR780. Sample 9/06IDTs SiS Desktop SolutionsSiS 662Reference design solutions 9LPR600 + 9P935SiS 656FXReference design solutions 953401+ 9P951 or 9P931SiS 649Reference design solutions 953401+ 9P935SiS 771/756/761Reference design solutions 953805Thank you